View CY22701_4147706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
CY22701
1 PLL In-System Programmable Clock Generator
Features
* In-system programmable through I2C Serial Programming Interface (SPI) * Programmable SRAM and non-volatile EEPROM memory bits with 3.3V supply * Integrated, phase-locked loop with programmable P and Q counters, output dividers * Low-jitter, high-accuracy outputs * 3.3V Operation * 8-lead SOIC
Benefits
* Custom timing solutions for designs not suitable for factory custom silicon, Xtals, or ASICs for production * Program and optimize designs while chip is on system board * Programming voltages contained in chip * High-performance PLL enables control of output frequencies that are customizable to support a wide range of applications * Meets critical timing requirements in complex system designs * Meets industry-standard voltage platforms * Industry standard packaging saves on board space
Part Number CY22701
No. of Outputs 2
Input Frequency Range
Output Frequency Range
1 - 167 MHz (Driven Clock Input) {Commercial} 80 kHz - 200 MHz (3.3V) {Commercial} 1 -150 MHz (Driven Clock Input) {Industrial} 80 kHz -167 MHz (3.3V) {Industrial} 8 - 30 MHz (Crystal Reference) {Comm. or Ind.}
Logic Block Diagram
XIN XOUT OUTPUT DIVIDERS Output Crosspoint Switch Array
OSC
Q
VCO P PLL
CLK1 CLK2
Clock Configuration
EEPROM Memory Array
Pin Configuration
WP [I2C- SPI:] SCL SDAT
XIN VDD
VDD VSS
1 2 3 4
8 XOUT CY22701 7 CLK2/WP 6 CLK1 5 SCL 8 PIN SOIC
SDA VSS
Cypress Semiconductor Corporation Document #: 38-07698 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised February 8, 2005
PRELIMINARY
Pin Description
Name XIN VDD SDAT VSS SCL CLK1 CLK2/WP XOUT[1] Pin Number 1 2 3 4 5 6 7 8 Description Reference crystal input 3.3V voltage supply Data input for serial programming Ground Clock signal input for serial programming Clock output 1 (Default to reference frequency) Clock output 2/Write Protect (Default Write Protect) Reference crystal output
CY22701
Functional Description
The CY22701 uses an EEPROM array along with on-chip programming voltages to program the device for development, or in production on the circuit board. An industry standard I2C serial programming interface (SPI) is used to program the scratchpad and clock core. Clock Features The programmable clock core is configured with the following features: * Crystal Oscillator: Programmable drive and load, support for external references up to 167 MHz. See Reference Frequency (REF) on page 4 * PLL: Programmable P, Q, offset, and loop filter parameters. * Outputs: 2 outputs and two programmable linear dividers. The output swing of CLK1 and 2 is set by VDD (3.3V). Clock configuration is stored in a dedicated 2-kbit block of nonvolatile EEPROM and a 2-kbit block of volatile SRAM. The SPI is used to write new configuration data to the on-chip programmable registers that are defined within the clock configuration memory blocks. Serial Programming Interface (SPI) The SPI uses industry-standard signaling in both standard and fast modes to program the 2-kbit EEPROM dedicated to clock configuration, and the 2-kbit SRAM block. See sections beginning with Using the Serial Programming Interface on page 2 for more information.
* Pin 7 is configured as Write Protect (see "Write Protect (WP) Registers" section on page 5 to configure as CLK2) This default clock configuration is typically customized to meet the needs of a specific application. It provides a clock signal upon power-on, to facilitate in-system programming. Alternatively, the CY22701 may be programmed with a different clock configuration prior to placement of the CY22701 in systems. While you can develop your own subroutine to program any or all of the individual registers described in the following pages, it may be easier to use CyberClocksTM to produce the required register setting file.
Using the Serial Programming Interface
The CY22701 provides an industry-standard serial programming interface for volatile and nonvolatile, in-system programming of unique frequencies and options. Serial programming and reprogramming allows for quick design changes and product enhancements, eliminates inventory of old design parts, and simplifies manufacturing. The CY22701 is a group of two slave devices with addresses as shown in Figure 1. The serial programming interface address of the CY22701 clock configuration 2-kbit EEPROM block is 68H. The serial programming interface address of the CY22701 clock configuration 2-kbit SRAM block is 69H. Should there be a conflict with any other devices in your system, both device addresses can also be changed using CyberClocks. Registers in the clock configuration 2-kbit SRAM memory block are written, when the user wants to update the clock configuration for on-the-fly changes. Registers in the clock configuration EEPROM block are written, if the user wants to update the clock configuration so that it is saved and used again after power-up or reset. All programmable registers in the CY22701 are addressed with eight bits and contain eight bits of data. Table 1 lists the specific register definitions and their allowable values. See section Serial Programming Interface Timing on page 10, for a detailed description.
Default Start-up Condition for CY22701
The default clock configuration is: * The crystal oscillator circuit is active. * CLK1 outputs REF frequency.
clock config. EE block 256 x 8 bits Address: 1101000
clock config. SRAM 256 x 8 bits Address: 1101001
Figure 1. Device Addresses for EEPROM and SRAM Clock Configuration Blocks
Note: 1. Float XOUT if XIN is externally driven.
Document #: 38-07698 Rev. *B
Page 2 of 15
PRELIMINARY
Table 1. Summary Table - CY22701 Programmable Registers Register 09H OCH 11H 12H 13H 40H 41H 42H 45H 47H Description CLKOE control DIV1SRC mux and DIV1N divider Write Protect registers Input crystal oscillator drive control Input load capacitor control Charge Pump and PB counter PO counter, Q counter Crosspoint switch matrix control DIV2SRC mux and DIV2N divider D7 0 D6 0 D5 0 D4 CLK2 D3 CLK1 D2 0
CY22701
D1 0 D0 0
DIV1SRC DIV1N(6) DIV1N(5) DIV1N(4) DIV1N(3) DIV1N(2) DIV1N(1) DIV1N(0) 0 0 CapLoad (7) 1 PB(7) PO 1 0 0 CapLoad (6) 1 PB(6) Q(6) 0 XCapSrc default=1 CapLoad (5) 0 PB(5) Q(5) 0 XDRV(1) CapLoad (4) Pump(2) PB(4) Q(4) WPSrc Default=0 XDRV(0) CapLoad (3) Pump(1) PB(3) Q(3) 1 0 CapLoad (2) Pump(0) PB(2) Q(2) 0 0 CapLoad (1) PB(9) PB(1) Q(1) 0 0 CapLoad (0) PB(8) PB(0) Q(0) 1
CLKSRC2 CLKSRC1 CLKSRC0 CLKSRC2 CLKSRC1 CLKSRC0 for CLK1 for CLK1 for CLK1 for CLK2 for CLK2 for CLK2
DIV2SRC DIV2N(6) DIV2N(5) DIV2N(4) DIV2N(3) DIV2N(2) DIV2N(1) DIV2N(0) CLK = ((REF * Ptotal)/Qtotal)/Post Divider CLK = REF/Post Divider CLK = REF The basic PLL block diagram is shown in Figure 2. Each of the two clock outputs on the CY22701 has a total of seven output options available to it. There are six post divider options available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N and DIV2N are independently calculated and are applied to individual output groups. The post divider options can be applied to the calculated VCO frequency ((REF*P)/Q) or to the reference frequency directly. In addition to the six post divider output options, the seventh option bypasses the PLL and passes the reference frequency directly to the crosspoint switch matrix.
CLKSRC Crosspoint Switch Matrix /DIV1N [45H]
CY22701 Frequency Calculation and Register Definitions
The CY22701 is an extremely flexible clock generator with three basic variables that can be used to determine the final output frequency: 1. Input reference frequency (REF) 2. the internally calculated P and Q dividers 3. Post divider, which can be a fixed or calculated value. There are three basic formulas for determining the final output frequency of a CY22701-based design. Any one of these three formulas may be used:
DIV1N [OCH] DIV1SRC [OCH]
1
Qtotal
CLK1
DIV1CLK
REF
(Q+2)
[42H]
PFD
VCO
Ptotal
0
/2
(2(PB+4)+PO)
[40H], [41H], [42H]
1
/3
Divider Bank 1 Divider Bank 2
/4 /2
/DIV2N [45H]
DIV2CLK
0
CLK2
DIV2SRC [47H] DIV2N [47H]
Figure 2. Basic Block Diagram of CY22701 PLL Document #: 38-07698 Rev. *B Page 3 of 15
PRELIMINARY
Reference Frequency (REF)
The reference frequency can be a crystal or a driven frequency. For crystals, the frequency range must be between 8 MHz and 30 MHz. For a driven frequency, the frequency range must be between 1 MHz and 167 MHz (Commercial Temp.) or 150 MHz (Industrial Temp.). Using a Crystal as the Reference Input The input crystal oscillator of the CY22701 is an important feature because of the flexibility it allows the user in selecting a crystal as a reference frequency source. The input oscillator has programmable gain, allowing for maximum compatibility with a reference crystal, regardless of manufacturer, process, performance and quality. Programmable Crystal Input Oscillator Gain Settings The Input crystal oscillator gain (XDRV) is controlled by two bits in register 12H, and are set according to Table 2. The parameters controlling the gain are the crystal frequency, the internal crystal parasitic resistance (ESR, available from the manufacturer), and the CapLoad setting during crystal start-up. Bits 3 and 4 of register 12H control the input crystal oscillator gain setting. Bit 4 is the MSB of the setting, and bit 3 is the LSB. The setting is programmed according to Table 2. All other bits in the register are reserved and should be programmed LOW. See Table 3 for bit locations and values. Using an External Clock as the Reference Input The CY22701 can also accept an external clock as reference, with speeds up to 167 MHz (or 150 MHz at Industrial Temp.). With an external clock, the XDRV (register 12H) bits must be set according to Table 4. Table 2. Programmable Crystal Input Oscillator Gain Settings Calculated CapLoad Value Crystal ESR Crystal Input Frequency 8 - 15 MHz 15 - 20 MHz 20 - 25 MHz 25 - 30 MHz 00 01 01 10 00H - 20H 30 60 01 10 10 10 01 01 10 10 20H - 30H 30 60 10 10 10 11 01 10 10 11 Input Load Capacitors
CY22701
Input load capacitors allow the user to set the load capacitance of the CY22701 to match the input load capacitance from a crystal. The value of the input load capacitors is determined by 8 bits in a programmable register [13H]. The proper CapLoad register setting is determined by the formula: CapLoad = (CL- CBRD - CCHIP)/0.09375 pF where: * CL = specified load capacitance of your crystal. * CBRD = the total board capacitance, due to external capacitors and board trace capacitance. In CyberClocks, this value defaults to 2 pF. * CCHIP = 6 pF. * 0.09375 pF = the step resolution available due to the 8-bit register. In CyberClocks, only the crystal capacitance (CL) is specified. CCHIP is set to 6 pF, and CBRD defaults to 2 pF. If your board capacitance is higher or lower than 2 pF, the formula above can be used to calculate a new CapLoad value and programmed into register 13H. In CyberClocks, enter the crystal capacitance (CL). The value of CapLoad will be determined automatically and programmed into the CY22701. Through the SDAT and SCLK pins, the value can be adjusted up or down if your board capacitance is greater or less than 2 pF. For an external clock source, CapLoad defaults to 1. See Table 5 for CapLoad bit locations and values. The input load capacitors are placed on the CY22701 die to reduce external component cost. These capacitors are true parallel-plate capacitors, designed to reduce the frequency shift that occurs when non-linear load capacitance is affected by load, bias, supply and temperature changes.
30H - 40H 30 60 10 10 11 N/A
Table 3. Register Map for Input Crystal Oscillator Gain Setting Address 12H
.
D7 0
D6 0
D5 XCapSrc, default=1
D4
D3
D2 0
D1 0
D0 0
XDRV(1) XDRV(0)
Table 4. Programmable External Reference Input Oscillator Drive Settings Reference Frequency Drive Setting 1-25 MHz 00 25-50 MHz 01 50-90 MHz 10 90-167 MHz 11
Table 5. Input Load Capacitor Register Bit Setting Address 13H D7 D6 D5 D4 D3 D2 D1 D0 CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
Document #: 38-07698 Rev. *B
Page 4 of 15
PRELIMINARY
DCXO
The default clock configuration of the CY22701 has 256 stored values that are used to adjust the frequency of the crystal oscillator, by changing the load capacitance. In order to use these stored values, the clock configuration must be reprogrammed to enable the DCXO feature. To Configure for DCXO Operation * XCapSrc, Register 12H[5] = 0 * XDRV[1:0], Register 12H[4:3] = (see Table 2) Once the clock configuration block is programmed for DCXO operation, the SPI may be used to dynamically change the capacitor load value on the crystal. A change in crystal load capacitance corresponds with a change in the reference frequency. Thus, the crystal oscillator frequency can be adjusted from -150 ppm of the nominal frequency value to +150 ppm of the nominal frequency value. "Nominal frequency - 150 ppm" is achieved by writing 00000000 into the CapLoad register, and "nominal frequency + 150 ppm" is achieved by writing 11111111 into the CapLoad register
CY22701
PLL Frequency, Q Counter
The first counter is known as the Q counter. The Q counter divides REF by its calculated value. Q is a 7-bit variable with a maximum value of 127 and minimum value of 0. The primary value of Q is determined by 7 bits in register 42H (6..0), but 2 is added to this register value to achieve the total Q, or Qtotal. Qtotal is defined by the formula: Qtotal = Q + 2. The minimum value of Qtotal is 2. The maximum value of Qtotal is 129. Register 42H is defined in Table 6. Stable operation of the CY22701 cannot be guaranteed if REF/Qtotal falls below 250 kHz. Qtotal bit locations and values are defined in Table 6.
PLL Frequency, P Counter
The next counter definition is the P (product) counter. The P counter is multiplied with the (REF/Qtotal) value to achieve the VCO frequency. The product counter, defined as Ptotal, is made up of two internal variables, PB and PO. The formula for calculating Ptotal is: Ptotal = (2(PB + 4) + PO) PB is a 10-bit variable, defined by registers 40H(1:0) and 41H(7:0). The 2 LSBs of register 40H are the two MSBs of variable PB. Bits 4..2 of register 40H are used to determine the charge pump settings (see section, Charge Pump Settings [40H(2..0)] on page 6"). The 3 MSBs of register 40H are preset and reserved and cannot be changed. PO is a single bit variable, defined in register 42H(7). This allows for odd numbers in Ptotal. The remaining 7 bits of 42H are used to define the Q counter, as shown in Table 6. The minimum value of Ptotal is 8. The maximum value of Ptotal is 2055. To achieve the minimum value of Ptotal, PB and PO should both be programmed to 0. To achieve the maximum value of Ptotal, PB should be programmed to 1023, and PO should be programmed to 1. Stable operation of the CY22701 cannot be guaranteed if the value of (Ptotal*(REF/Qtotal)) is above 400 MHz or below 100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
Write Protect (WP) Registers
To reconfigure pin 7 as WP, to control enable/disable of write protection, use the SPI to write the following: WPSrc, Register 11H[3] = 0 CLK2, Register 09H[4] = 0 CLKSRC 2,1,0, Register 45H[3:1] = 111 When active (WP = 1), WP prevents the control logic for the EE from initiating a erase/program cycle for the EEPROM blocks. All serial shifting works as normal. To reconfigure pin 7 as CLK2, use the SPI to write the following: WPSrc, Register 11H[3] = 1 CLK2, Register 09H[4] = 1 CLKSRC 2,1,0, Registers 45H[3:1] = see Table 11
Table 6. Q Counter Register Definition Register 42H D7 PO D6 Q(6) D5 Q(5) D4 Q(4) D3 Q(3) D2 Q(2) D1 Q(1) D0 Q(0)
Table 7. P Counter Register Definition Address 40H 41H 42H D7 1 PB(7) PO D6 1 PB(6) Q(6) D5 0 PB(5) Q(5) D4 Pump(2) PB(4) Q(4) D3 Pump(1) PB(3) Q(3) D2 Pump(0) PB(2) Q(2) D1 PB(9) PB(1) Q(1) D0 PB(8) PB(0) Q(0)
Document #: 38-07698 Rev. *B
Page 5 of 15
PRELIMINARY
Table 8. PLL Post Divider Options Address OCH 47H D7 DIV1SRC DIV2SRC D6 DIV1N(6) DIV2N(6) D5 DIV1N(5) DIV2N(5) D4 DIV1N(4) DIV2N(4) D3 DIV1N(3) DIV2N(3) D2 DIV1N(2) DIV2N(2) D1 DIV1N(1) DIV2N(1)
CY22701
D0 DIV1N(0) DIV2N(0)
PLL Post Divider Options
The output of the VCO is routed through two independent muxes, then to two divider banks to determine the final clock output frequency. The mux determines if the clock signal feeding into the divider banks is the calculated VCO frequency or REF. There are 2 select muxes (DIV1SRC and DIV2SRC) and 2 divider banks (Divider Bank 1 and Divider Bank 2) used to determine this clock signal. The clock signals passing through DIV1SRC and DIV2SRC are referred to as DIV1CLK and DIV2CLK, respectively. The divider banks have 4 unique divider options available: /2, /3, /4, and /DIVxN. DIVxN is a variable that can be independently programmed (DIV1N and DIV2N) for each of the 2 divider banks. The minimum value of DIVxN is 4. The maximum value of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to work properly. DIV1SRC is a single bit variable, controlled by register OCH. The remaining 7 bits of register OCH determine the value of post divider DIV1N. DIV2SRC is a single bit variable, controlled by register 47H. The remaining 7 bits of register 47H determine the value of post divider DIV2N. Register OCH and 47H are defined in Table 8.
are dependent on internal variable PB (see section [00H to 08H] - Reserved [0AH to 0BH] - Reserved [0DH to 10H] -Reserved [14H to 3FH] -Reserved [43H to 44H] -Reserved [48H to FFH] -Reserved [46H] -Reserved on page 7). Table 9 summarizes the proper charge pump settings, based on Ptotal. See Table 10, Register 40H Change Pump Bit Settings on page 6, for register 40H bit locations. Although using Table 10 will guarantee stability, it is recommended to use the Print Preview function in CyberClocksTM to determine the ideal charge pump settings for optimal jitter performance. PLL stability cannot be guaranteed for Ptotal values below 16 and above 1023. If Ptotal values above 1023 are needed, use CyberClocks to determine the best charge pump setting. Table 9. Charge Pump Settings Charge Pump Setting - Pump(2..0) 000 001 010 011 100 101, 110, 111 Calculated Ptotal 16-44 45-479 480-639 640-799 800-1023 Do Not Use - device will be unstable
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge pump settings are controlled by bits (4..2) of register 40H, and Table 10.Register 40H Change Pump Bit Settings Address 40H D7 1 D6 1 D5 0 D4 Pump(2)
D3 Pump(1)
D2 Pump(0)
D1 PB(9)
D0 PB(8)
Document #: 38-07698 Rev. *B
Page 6 of 15
PRELIMINARY
Clock Output Settings
CLKSRC - Clock Output Crosspoint Switch Matrix [45H(7..0)] Both clock output can be defined to come from one of seven unique frequency sources. The CLKSRC(2..0) crosspoint switch matrix defines which source is attached to each individual clock output. CLKSRC(2..0) is set in Registers 45H. When DIV1N is divisible by guaranteed to be rising CLKSRC(0,0,1). When DIV1N guaranteed to be rising CLKSRC(0,0,1). 4, then CLKSRC(0,1,0) is edge phase-aligned with is 6, then CLKSRC(0,1,1) is edge phase-aligned with
CY22701
CLKOE - Clock Output Enable Control [09H(7..0)] Each clock output has its own output enable, CLKOE, controlled by register 09H(7..0). To enable an output, set the corresponding CLKOE bit to 1. CLKOE settings are in Table 13. Test, Reserved, and Blank Registers Writing to any of the following registers will cause the part to exhibit abnormal behavior: [00H to 08H] - Reserved [0AH to 0BH] - Reserved [0DH to 10H] -Reserved [14H to 3FH] -Reserved [43H to 44H] -Reserved [48H to FFH] -Reserved [46H] -Reserved
When DIV2N is divisible by 4, then CLKSRC(1,0,1) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). When DIV2N is divisible by 8, then CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned with CLKSRC(1,0,0). Table 11.Clock Output Settings - Clock Source CLKSRC[2:0] CLKSRC2 0 0 0 0 1 1 1 1 CLKSRC1 0 0 1 1 0 0 1 1 CLKSRC0 0 1 0 1 0 1 0 1 Reference Input
Definition and Notes DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4 to 127. If Divider Bank 1 is not being used, set DIV1N to 8 DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4. DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6. DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4 to 127. If Divider Bank 2 is not being used, set DIV2N to 8. DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4. DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8. Reserved - Do not use
Table 12.CLKSRC Registers Address 45H D7 1 D6 CLKSRC2 for CLK1 D5 CLKSRC1 for CLK1 D4 CLKSRC0 for CLK1 D3 CLKSRC2 for CLK2 D2 CLKSRC1 for CLK2 D1 CLKSRC0 for CLK2 D0 1
Table 13.CLKOE Bit Setting Address 09H D7 0 D6 0 D5 0 D4 CLKOE for CLK2 D3 CLKOE for CLK1 D2 0 D1 0 0
Document #: 38-07698 Rev. *B
Page 7 of 15
PRELIMINARY
Serial Programming Interface (SPI) Protocol and Timing
The CY22701 utilizes a 2-serial-wire interface SDAT and SCLK that operates up to 400 kbits/sec in Read or Write mode. The basic Write serial format is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; etc. until STOP Bit. The basic serial format is illustrated in Figure 4. Data Valid Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW as illustrated in Figure 5. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 6. Start Sequence - Start Frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (7 bits) and a R/W bit, followed by register address (8 bits) and register data (8 bits). Stop Sequence - Stop Frame is indicated by SDAT going HIGH when SCLK is HIGH. A Stop Frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write Mode the CY22701 will respond with an Acknowledge pulse after every 8 bits. This is accomplished by pulling the SDAT line LOW during the N*9th clock cycle as illustrated in Figure 7. (N = the number of bytes transmitted). During Read Mode the acknowledge pulse after the data packet is sent is generated by the master. Writing Multiple Bytes
CY22701
The CY22701 is capable of receiving up to 16 consecutive written bytes. In order to write more than one byte at a time, the device addressing the EEPROM does not end the write sequence with a stop condition. Instead, the device can send up to fifteen more bytes of data to be stored. After each byte, the EEPROM responds with an acknowledge bit, just like after the first byte. The EEPROM will accept data until the acknowledge bit is responded to by the stop condition, at which time it enters the internal write process as described in the section above. When receiving multiple bytes, the CY22701 internally increments the address of the last 4 bits in the address word. After 16 bytes are written, that incrementing brings it back to the first word that was written. If more than 16 bytes are written, the CY22701 will overwrite the first bytes written.
Read Operations
Read operations are initiated the same way as Write operations except that the R/W bit of the slave address is set to `1' (HIGH). There are three basic read operations: current address read, random read, and sequential read. Current Address Read The CY22701 has an onboard address counter that retains 1 more than the address of the last word access. If the last word written or read was word `n,' then a current address read operation would return the value stored in location `n+1'. When the CY22701 receives the slave address with the R/W bit set to a `1,' the CY22701 issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY22701 to stop transmission. Random Read Through random read operations, the master may access any memory location. To perform this type of read operation, first the word address must be set. This is accomplished by sending the address to the CY22701 as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next the master reissues the control byte with the R/W byte set to `1.' The CY22701 then issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition which causes the CY22701 to stop transmission. Sequential Read Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmission of the first 8-bit data word. This action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master may serially read the entire contents of the memory blocks. Similarly, sequential reads within either the EEPROM or SRAM clock configuration blocks will wrap within the block to the first word of the same block after reaching the end of either block.
Device Addressing
The first seven bits of the device address word for the clock configuration EEPROM block are 1101000. The first seven bits of the device address word for the clock configuration SRAM block are 1101001. The final bit of the address specifies the operation (HIGH/1 = Read, LOW/0 = Write)
Write Operations
Writing Individual Bytes A valid write operation must have a full 8-bit word address after the device address word, which is followed by an acknowledgment bit from the EEPROM (ack = 0/LOW). The next 8 bits must contain the data word intended for storage. After the data word is received, the EEPROM responds with another acknowledge bit (ack = 0/LOW), and the device that is addressing the EEPROM must end the write sequence with a stop condition. The EEPROM now enters an internal write process transferring the data received to nonvolatile memory. During, and until completion of, this internal write process, the EEPROM will not respond to other commands.
Document #: 38-07698 Rev. *B
Page 8 of 15
PRELIMINARY
SCL
CY22701
SDAT
Address or Acknowledge Valid Data may be changed STOP Condition
START Condition
Figure 3. Data Transfer Sequence on the Serial Bus
1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 1 Bit Slave ACK 1 Bit Slave ACK 8-bit Register Data (XXH+1) 1 Bit Slave ACK 8-bit Register Data (XXH+2) 1 Bit Slave ACK 8-bit Register Data (XXH) 1 Bit Slave ACK 1 Bit Slave ACK 1 Bit Slave ACK
SDAT Write
Multiple Contiguous Registers
Start Signal
8-bit Register Address (XXH)
8-bit Register Data (XXH)
8-bit Register Data (X0H) Stop Signal
16 byte wrap
SDAT Read
Current Address Read
Start Signal
1 Bit 1 Bit Slave R/W = 1 ACK 7-bit Device Address
1 Bit Slave ACK
1 Bit Master ACK
8-bit Register Data Stop Signal
SDAT Read
Multiple Contiguous Registers
Start Signal
1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address
1 Bit Slave ACK
1 Bit Master ACK 8-bit Register Data (XXH)
1 Bit Master ACK 8-bit Register Data (XXH+1)
1 Bit Master ACK 8-bit Register Data (8FFH)
1 Bit Master ACK
1 Bit Master ACK
1 Bit Master ACK
8-bit Register Address (XXH)
7-bit Device Address +R/W=1
8-bit Register Data (000H) Stop Signal
Repeated Start bit
Figure 4. Data Frame Architecture
Data Valid Transition to next Bit
SDAT
tDH CLKHIGH VIH
tSU
SCLK
VIL
CLKLOW
Figure 5. Data Valid and Data Transition Periods
Document #: 38-07698 Rev. *B
Page 9 of 15
PRELIMINARY
Serial Programming Interface Timing
CY22701
SDAT
START
Transition to next Bit
SCLK
STOP
Figure 6. Start and Stop Frame
SDAT +
START DA6 DA5 DA0 R/W ACK RA7
+
RA6 RA1 RA0 ACK D7 D6
+
D1 D0 ACK STOP
+ SCLK
+
+
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data) Table 14.Recommended Pullable Crystal Specifications Parameter CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Min. - - 3 - 400 - - 180 14.4 Typ. 14 - - 0.5 - - - - 18 Max. - 25 - 2 - -200 7 250 21.6 fF mW ppm ppm pF Units pF
Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance
Document #: 38-07698 Rev. *B
Page 10 of 15
PRELIMINARY
Absolute Maximum Conditions
Parameter VDD TS TJ Description Supply Voltage Storage Temperature Junction Temperature Logic Inputs I2 C interface (SDAT and SCL) Digital Outputs referred to VDD Electro-Static Discharge Endurance (@ 25C) Data retention 10 Min. -0.5 -65 -40 VSS - 0.5 -0.5 VSS - 0.5 Max. 7.0 125 100 VDD + 0.5 5.5 VDD + 0.5 2000 1,000,000 (100k/page)
CY22701
Unit V C C V V V V writes yrs
Recommended Operating Conditions
Parameter VDD TA TA CLOAD tPU Operating Voltage Ambient Temperature, Industrial grade Ambient Temperature, Commercial grade Max. Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.135 -40 0 - 0.05 Typ. 3.3 - - - - Max. 3.465 85 70 15 500 Unit V C C pF ms
DC Electrical Specifications
Parameter IOH IOL VIH VIL CIN IIZ fXO IVDD ISB Name Output High Current[2] Output Low Current[2] Input High Voltage Input Low Voltage Input Capacitance[2, 3] Except XTAL pins Input Leakage Current VCXO Pullability Range[3] Supply Current Supply Current - Power Down Mode Enabled Current drawn while part is in standby. Description VOH = VDD - 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V CMOS levels CMOS levels Min. 12 12 0.7 * VDD - - - +150 - - Typ. - - - - - - - 45 5 Max. 24 24 - 0.3 * VDD 7 10 - - 40 Unit mA mA V V pF A ppm mA A
DC Electrical Specifications - 2.5V Outputs
Parameter IOH2.5 IOL2.5 Name Output High Current[2, 4] Current[2, 4] Description VOH = VDD - 0.5, VDD = 3.3 V Min. 12 Typ. - - Max. 24 24 Unit mA mA
Output Low VOL = 0.5, VDD = 3.3 V 12 Notes: 2. Guaranteed by design, not 100% tested. 3. Crystal must meet Table 14 specifications. 4. VDD is only specified and characterized at 3.3V + 5%. VDDL may be powered at any value between 3.465 and 2.375.
Document #: 38-07698 Rev. *B
Page 11 of 15
PRELIMINARY
AC Electrical Specifications (VDD = 3.3V)
Parameter[5] DC Name Clock Output Duty Cycle Description fOUT < 150 MHz fOUT > 150 MHz, or fOUT = fREF See Figure 8 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 9. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 9. For related clock outputs Maximum absolute jitter (EEPROM quiet) (during EEPROM reads) (during EEPROM writes) Ramp time from 1.5V to 2.5V
[6]
CY22701
Min. 45 40 0.8 0.8 - - Typ. 50 50 1.4 1.4 - 250 300 350 - - 20 - Max. 55 60 - - 250 - Unit %
ERO EFO t5 t9
Rising Edge Rate Falling Edge Rate Output to Output Skew Clock Jitter
V/ns V/ns ps ps
t10 tVDDramp
PLL Lock Time Power Supply Ramp
-
60 15 -
ms ms ms
tVDDpowerdown Power Supply Power Down Wait time after a write to EEPROM is initiated after Write by the stop bit until VDD fails below 2.5V Memory Section Specifications FSCL tL tH tSP tAA tBUFF SCL input frequency Clock Pulse Low Clock Pulse High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission may start Start Hold Time Start Set-up Time Data in Hold Time Data in Set-up time Inputs rise time Inputs fall time Stop Set-up Time Data Out Hold Time Write Cycle Time CLKLOW, 20-80% of VDD CLKHIGH, 80-20% of VDD Square noise spike on input
- 1.3 0.6 - 0.1 1.2 - - - - -
400 - - 50 0.9 -
kHz s s ns s s
tHDSTART tSUSTART tDH tSU tRI tFI tSUSTOP tDH tWR
0.6 0.6 0 100 - - 0.6 50 -
- - - - - - - - -
- - - - 300 300 - - 20
s s ms ns ns ns s ns ms
Test and Measurement Set-up VDD 0.1 F OUTPUTS CLK out CLOAD
GND
Notes: 5. Not 100% tested. 6. The power supply voltage must increase monotonically from 0 to 2.5V; once VDD reaches 1.5V, it must ramp to 2.5V within 15 ms.
Document #: 38-07698 Rev. *B
Page 12 of 15
PRELIMINARY
Voltage and Timing Definitions
CY22701
Figure 8. Duty Cycle Definition; DC = t2/t1
Figure 9. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
Ordering Information
Ordering Code CY22701FSXC CY22701FSXCT CY22701FSXI CY22701FSXIT Feature Field Programmable Field Programmable Field Programmable Field Programmable Package Name Lead Free SOIC Lead Free SOIC - Tape and Reel Lead Free SOIC Lead Free SOIC - Tape and Reel Package Type 8 Pin SOIC 8 Pin SOIC 8 Pin SOIC 8 Pin SOIC Operating Range Commercial Commercial Industrial Industrial Operating Voltage 3.3V 3.3V 3.3V 3.3V
Document #: 38-07698 Rev. *B
Page 13 of 15
PRELIMINARY
Package Drawing and Dimensions
8 Lead (150 Mil) SOIC - S08 (150-Mil) SOIC S8 8-lead
PIN 1 ID
CY22701
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names mentioned in this document may be the trademarks of their respective holders. CyberClocks is a trademark of Cypress Semiconductor Corporation.
Document #: 38-07698 Rev. *B
Page 14 of 15
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY22701 1 PLL In-System Programmable Clock Generator Document Number: 38-07698 REV. ** *A *B ECN NO. Issue Date 226712 318313 320154 See ECN See ECN See ECN Orig. of Change RGL RGL LPG Description of Change New data sheet
CY22701
swapped CLK2 to CLK1 in Summary and CLKOE Bit Setting Tables. Minor Change - Correct footer
Document #: 38-07698 Rev. *B
Page 15 of 15

▲Up To Search▲

Price & Availability of CY22701

	To Download CY22701 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .